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ic-lfh series high-resolution linear image sensors rev b1, page 1/ 14 features 1024/960/640/320 active photo pixels with 12.7 m x 600 m (2000 dpi) pin-selectable resolution of 2000, 1000, 500 and 250 dpi (binning or averaging selectable) integrating l-v conversion followed by a sample & hold circuit high sensitivity and uniformity over wavelength high pixel clock rate of up to 5 mhz asynchronous, global shutter enables fexible integration times 3 v capable analogue output with separate supply pin push-pull output amplifer applications triangulation sensors contact image sensors ccd replacement packages obga lfh1c obga lfh2c obga lfh3c obga lfh5c block diagram copyright ? 2016, 2017 ic-haus http://www.ichaus.com p r e l i m i n a r y p r e l i m i n a r y dra_lfh1c-lfh320_0_pack_2a, 2:1 drb_lfh2c-lfh640_0_pack_2a, 2:1 drb_lfh3c-lfh960_0_pack_2a, 2:1 dra_lfh5c-lfh1024_z_pack_2a, 2:1 ic-lfhxxx power down reset output amplifier sample & hold read pixel averaging binning/ control control pixel 1 pixel 2 ... n 4 3 bna clk gnd gnda vdda vdd vao res0 esh ao si res1 nres
ic-lfh series high-resolution linear image sensors rev b1, page 2/ 14 description ic-lfh series are integrating light-to-voltage convert- ers with 1024/960/640/320 pixels pitched at 12.7 m (center-to-center distance). each pixel consists of a 12.7 m x 600 m photodiode, an integration capaci- tor, and a sample-and-hold circuit. the control logic makes operation very easy, with only a start and clock signal necessary. a third input (esh) optionally controls the asynchronous, global shutter. when the start signal is given, a new integration phase is initiated. nine clocks are requiered to sample the current integration value and to reset the integration capacitor. after further 7 clocks, while the internal dark level voltage (vmin) is output at ao, the value of the pixel #1 can be read out. with further clocks the following pixel voltages are output. the complete line sensor is read out after 1040/976/656/336 clock pulses respectively. ic-lfhxxx is suitable for high pixel clock rates of up to 5 mhz. packaging information pin configuration lfh1c pin functions no. name function a1 res0 select resolution bit 0 a2 res1 select resolution bit 1 a3 vao pixel output supply voltage a4 ao analog pixel output b1 vdd digital supply +5 v b2 n/c b3 n/c b4 vdda analog supply +5 v c1 etp enable test mode* c2 gnd digital ground c3 gnda analog ground c4 nres power-down reset output (low active) d1 clk clock d2 si start of integration d3 esh enable shutter d4 bna select binning/averaging *etp must be connected to gnd/gnda p r e l i m i n a r y p r e l i m i n a r y drb_lfh1c-lfh320_0_pack_3c, 5:1 4 a d c b 1 2 3
ic-lfh series high-resolution linear image sensors rev b1, page 3/ 14 pin configuration lfh2c pin functions no. name function 1 res0 select resolution bit 0 2 res1 select resolution bit 1 3 vdd digital supply +5 v 4 gnd digital ground 5 etp enable test mode* 6 si start of integration 7 clk clock 8 bna select binning/averaging 9 esh enable shutter 10 nres power-down reset output (low active) 11 gnda analog ground 12 vdda analog supply +5 v 13 vao pixel output supply voltage 14 ao analog pixel output *etp must be connected to gnd/gnda pin configuration lfh3c pin functions no. name function 1 res0 select resolution bit 0 2 res1 select resolution bit 1 3 vdd digital supply +5 v 4 gnd digital ground 5 etp enable test mode* 6 si start of integration 7 clk clock 8 bna select binning/averaging 9 esh enable shutter 10 nres power-down reset output (low active) 11 gnda analog ground 12 vdda analog supply +5 v 13 vao pixel output supply voltage 14 ao analog pixel output *etp must be connected to gnd/gnda p r e l i m i n a r y p r e l i m i n a r y 1 8 9 10 11 12 13 7 6 5 4 3 2 14 drb_lfh2c-lfh640_0_pack_3c, 5:1 drb_lfh3c-lfh960_0_pack_3c, 5:1 1 2 3 4 5 6 7 8 9 14 13 12 11 10
ic-lfh series high-resolution linear image sensors rev b1, page 4/ 14 pin configuration lfh5c pin functions no. name function 1 res0 select resolution bit 0 2 res1 select resolution bit 1 3 vdd digital supply +5 v 4 gnd digital ground 5 etp enable test mode* 6 si start of integration 7 clk clock 8 bna select binning/averaging 9 esh enable shutter 10 nres power-down reset output (low active) 11 gnda analog ground 12 vdda analog supply +5 v 13 vao pixel output supply voltage 14 ao analog pixel output *etp must be connected to gnd/gnda p r e l i m i n a r y p r e l i m i n a r y dra_lfh5c-lfh1024_z_pack_3c, 5:1 1 2 3 4 5 6 7 8 9 14 13 12 11 10
ic-lfh series high-resolution linear image sensors rev b1, page 5/ 14 absolute maximum ratings beyond these values damage may occur; device operation is not guaranteed. item symbol parameter conditions unit no. min. max. g001 vdd digital supply voltage -0.3 6 v g002 vdda analog supply voltage -0.3 6 v g003 vao analog output ao supply voltage -0.3 6 g004 v() voltage at si, clk, esh, res0, res1, bna, etp -0.3 vdd + 0.3 v g005 i() current in ao -10 10 ma g006 vd() esd susceptibility at all pins hbm 100 pf, discharged through 1.5 k ? 4 kv g007 tj junction temperature -40 150 c g008 ts chip storage temperature -40 150 c thermal data operating conditions: vdda = vdd = 5 v 10 % item symbol parameter conditions unit no. min. typ. max. t01 ta operating ambient temperature see the relevant package specifcations all voltages are referenced to ground unless otherwise stated. all currents fowing into the device pins are positive; all currents fowing out of the device pins are negative. p r e l i m i n a r y p r e l i m i n a r y
ic-lfh series high-resolution linear image sensors rev b1, page 6/ 14 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -25...110 c unless otherwise noted item symbol parameter conditions unit no. min. typ. max. total device 001 vdd digital supply voltage range 4.5 5.5 v 002 vdda analog supply voltage range 4.5 5.5 v 003 i(vdd) supply current in vdd f(clk) = 1 mhz 300 a 004 i(vdda) supply current in vdda n = 320 11 15 ma n = 640 20 25 ma n = 960 26 30 ma n = 1024 28 32 ma 005 vc()hi clamp voltage hi at si, clk, esh, res0, res1, bna, etp, nres vc()hi = v() ? v(vdd), i() = 1 ma 0.3 1.8 v 006 vc()lo clamp voltage lo at si, clk, esh, res0, res1, bna, etp, nres vc()hi = v() ? v(gnda), i() = -1 ma -1.5 -0.3 v 007 vc()hi clamp voltage hi at ao vc()hi = v(ao) ? v(vao), i(ao) = 1 ma 0.3 1.5 v 008 vc()lo clamp voltage lo at ao, vdda, vdd, gnd vc()lo = v() ? v(gnda), i() = -1 ma -1.5 -0.3 v photodiode array 201 a() radiant sensitive area 600 m x 12.70 m, per pixel 0.00762 mm 2 203 ar spectral application range s( ar) = 0.25 x s( )max 420 980 nm analogue output ao, vao 301 v(vao) permissible input voltage g(ao) = 1 3 3.3 3.6 v g(ao) = 1.67 4.5 5.0 5.5 v 302 i(vao) supply current in vao 10 pf load at ao, f(clk) = 5 mhz; v(vao) = 3...3.6 v 2.5 ma v(vao) = 4.5...5.5 v 3 ma 303 g(ao) gain vao < th(vao) 0.9 1 1.1 vao > th(vao) 1.3 1.67 1.8 304 vt(vao)hi threshold voltage gain switch hi 3.7 4.6 v 305 vt(vao)lo threshold voltage gain switch lo 3.5 4.4 v 306 vt(vao)hys hysteresis gain switch 100 350 mv 308 vs(ao)hi saturation voltage hi vs(ao)hi = vao ? v(ao), i(ao) = -2 ma 120 250 mv 309 k sensitivity res1/0 = 00, = 775 nm; g(ao) = 1 0.9 v/pws g(ao) = 1.67 1.5 v/pws 311 kr sensitivity ratio k(binning ? 2) / k 1.8 k(binning ? 4) / k 3.3 k(binning ? 8) / k 4.7 k(averaging ? x) / k; x = 2, 4, 8 1 312 v0(ao) offset voltage integration time 1 ms, no illumination 100 200 500 mv 313 ? v0(ao) offset voltage deviation during integration mode ? v0(ao) = v(ao)t1 ? v(ao)t2, ? t = t2 ? t1 = 1 ms -150 150 mv 314 ? v(ao) signal deviation during hold mode ? v(ao) = v(ao)t1 ? v(ao)t2, ? t = t2 ? t1 = 1 ms -150 150 mv 315 tp(clk-ao) settling time cl(ao) = 10 pf, clk lo hi until v(ao) = 0.95 ? vs(ao)hi 200 ? ns 316 prnu pixel response nonuniformity v(ao) = 2.5 v 10 15 % 317 inl integral nonlinearity g(ao) = 1: v(ao) = 0.5...3.0 v, 1.5 ? % g(ao) = 1.67: v(ao) = 0.5...4.5 v 318 v noise (ao) output noise voltage v(ao) = 2.5 v 1.5 ? mv rms 319 dr dynamic range ? v(vao) = 5.0 v; v(ao) max = 5 v 70 db v(vao) = 3.3 v; v(ao) max = 3.3 v 66 db 320 v(ao)min output reference voltage 150 200 280 mv power-down reset nres 801 vddon power-on release by vdd 4.0 4.4 v p r e l i m i n a r y p r e l i m i n a r y
ic-lfh series high-resolution linear image sensors rev b1, page 7/ 14 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -25...110 c unless otherwise noted item symbol parameter conditions unit no. min. typ. max. 802 vddoff power-down reset by vdd 3.0 3.5 v 803 vddhys hysteresis vddhys = vddon ? vddoff 350 460 800 mv 804 vs()lo saturation voltage lo i() = 1.6 ma 0 0.3 v 805 vs()hi saturation voltage hi i() = -1.6 ma, vs()hi = vdd ? v() 0 0.3 v 806 isc()lo short current lo v() = lo and pin shorted with vdd 5 70 ma 807 isc()hi short current hi v() = hi and pin shorted with gnd -70 -5 ma ttl input interface bna, clk, esh, etp, res0, res1, si i01 vt()hi threshold voltage hi 2.0 v i02 vt()lo threshold voltage lo 0.8 v i03 vt()hys hysteresis vt()hys = vt()hi ? vt()lo 200 500 mv i04 i()pd pull-down current 5 30 70 a i05 fclk permissible clock frequency reset integration and digital control 10 mhz read pixel and s&h; n = 320 (0.3) ? 5 mhz n = 640 (0.6) ? 5 mhz n = 960, 1024 (1) ? 5 mhz optical characteristics: diagrams figure 1: relative spectral sensitivity ? projected values by sample characterization ? dr = 20 log v ( ao ) max ? v 0( ao ) max v noise ( ao ) ? relates to a 1 ms hold time; cf. electrcal characteristics nos. 313 and 314. p r e l i m i n a r y p r e l i m i n a r y
ic-lfh series high-resolution linear image sensors rev b1, page 8/ 14 operating requirements: integration and read control operating conditions: vdda = vdd = 4.5...5.5 v, gnda = gnd = 0 v, tj = -25...110 c item symbol parameter conditions unit no. min. max. integration and read control i001 t c permissible clock period clk 100 ns i002 t l1 clock signal clk hi-level duration 50 ns i003 t l2 clock signal clk lo-level duration 50 ns i004 t s1 setup time: si stable before clk lo hi 50 ns i005 t h1 hold time: si stable after clk lo hi 50 ns i006 t l3 shutter signal esh lo-level duration 100 ns figure 2: timing diagram figure 3: timing diagram shutter p r e l i m i n a r y p r e l i m i n a r y t l1 t l2 t c t s1 t h1 clk si si clk esh t l3 change forbidden change allowed forbidden 1 2 9
ic-lfh series high-resolution linear image sensors rev b1, page 9/ 14 description of functions pixel structure and resolution one pixel consist of a photodiode, an integration ca- pacitor, and an s&h stage. for reducing the resolution, the pixels can be grouped together by means of pins res1/0. changing the resolution can be achieved in two ways, binning or averaging. averaging does not change the sensitivity, whereas binning increases the sensitivity by the ratio given in the table on the right. pin bna selects the mode respectively. pins res1/0 state pin bna pixels resolution sensitivity ratio 1 0/0 - n pixels 2000 dpi 1 0/1 0 n/2 pixels 1000 dpi 1 1 n/2 pixels 1000 dpi 1.8 1/0 0 n/4 pixels 500 dpi 1 1 n/4 pixels 500 dpi 3.3 1/1 0 n/8 pixels 250 dpi 1 1 n/8 pixels 250 dpi 4.7 1 all pixels uniformly illuminated n = 320/640/960/1024 pixels figure 4: pixel structure with res1/0 = 00 figure 5: pixel structure with resolution change and averaging mode p r e l i m i n a r y p r e l i m i n a r y p i x e l 1 r e a d h o l d p i x e l 2 p i x e l 4 p i x e l 3 i n t e g r a t i o n e s h n r c i s & h s & h s & h s & h r d 1 r d 2 r d 3 r d 4 b n a r e s x v d d a p i x e l 1 r e a d h o l d p i x e l 2 p i x e l 4 p i x e l 3 i n t e g r a t i o n e s h n r c i s & h s & h s & h s & h r d 1 r d 2 r d 3 r d 4 b n a r e s x v d d a
ic-lfh series high-resolution linear image sensors rev b1, page 10/ 14 figure 6: pixel structure with resolution change and binning mode operation description following an internal power-on reset the integration and hold capacitors are discharged. a high signal at si and a rising edge at clk triggers a readout cycle and with it a new integration cycle. six clocks later the internal reset is done and the device is in integration mode. the readout of the analog pixel values starts with the 17 th clock pulse. operation with the shutter function integration can be suspended at any time via pin esh (asynchronous, global shutter), i.e. the photodiodes are disconnected from their corresponding integration ca- pacitor when esh is high and the current integration capacitor voltages are maintained. if this pin is open or switched to gnd, the pixel photocurrents are summed up by the integration capacitors until the next si signal. pins si clk esh ao vmin 1 2 n-1 n internal clk nr n+10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 n+15 n+16 1 2 read read int0 sample read int1 sample int int1 reset int2 figure 7: example integration and readout cycle p r e l i m i n a r y p r e l i m i n a r y p i x e l 1 r e a d h o l d p i x e l 2 p i x e l 4 p i x e l 3 i n t e g r a t i o n e s h n r c i s & h s & h s & h s & h r d 1 r d 2 r d 3 r d 4 b n a r e s x v d d a
ic-lfh series high-resolution linear image sensors rev b1, page 11/ 14 read control the readout of the analog pixel values is controlled by the followoing pins: ? pin si ? pin clk a rising clk edge with a hi value at si resets the inter- nal read out circuit, initiating a readout of the previously sampled pixel values. while clocking more then n clocks the read out will restart with pixel #1 without sampling. thus a non-destructive re-read is possible. pins si clk ao vmin 1 2 n-1 n vmin internal clk nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 n+15 n+16 1 2 state hold sample hold sample figure 8: complete readout cycle pins si clk ao vmin 1 2 vmin internal clk nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 state hold sample hold sample figure 9: interrupting the readout cycle pins si clk ao vmin 1 2 n-1 n 1 2 internal clk nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 n+15 n+16 n+17 n+18 state hold sample hold figure 10: non-destructive restart of readout cycle p r e l i m i n a r y p r e l i m i n a r y
ic-lfh series high-resolution linear image sensors rev b1, page 12/ 14 integration control the integration is controlled by the signals: ? pin si ? pin clk ? pin esh a new integration phase is started with a rising clk edge and si high. after 9 clocks a new integration cy- cle is initiated. with pin esh = lo all photodiodes are connected to the internal capacitors and the photodi- ode currents are integrated. the integration can be suspended by setting pin esh to hi, disconnecting the photodiodes from their integration capacitors. pins si clk esh ao vmin 1 2 n-1 n vmin internal clk nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 n+15 n+16 1 2 state int reset int figure 11: integration cycle pins si clk esh ao vmin 1 2 n-1 n vmin internal clk nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 n+15 n+16 1 2 state int reset int figure 12: integration cycle with shutter action pins si clk esh ao vmin 1 2 vmin internal clk nr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 state int reset int figure 13: integration cycle with shutter action and readout interrupt p r e l i m i n a r y p r e l i m i n a r y
ic-lfh series high-resolution linear image sensors rev b1, page 13/ 14 design review: function notes ic-lfhxxx 1 no. function, parameter/code description and application notes 1 sensitivity ratio with binning, electrical characteristics no. 309 gain increase in binning is lower than stated 2 settling time, electrical characteristics no. 314 dips in the pixel voltage slow down settling time table 5: notes on chip functions regarding ic-lfhxxx chip release 1 ic-lfhxxx z no. function, parameter/code description and application notes 1 binning/averaging binning/averaging cannot be used 2 settling time, electrical characteristics no. 314 dips in the pixel voltage slow down settling time table 6: notes on chip functions regarding ic-lfhxxx chip release z ic-lfhxxx z1 no. function, parameter/code description and application notes 1 settling time, electrical characteristics no. 314 dips in the pixel voltage slow down settling time table 7: notes on chip functions regarding ic-lfhxxx chip release z1 revision history rel. rel. date ? chapter modifcation page b1 2017-09-01 electrical characteristics operating conditions: tj = -25...110 c 6-7 electrical characteristics item no. 302 added 6 electrical characteristics item nos. 309, 311 corrected 6 electrical characteristics optical characteristics: diagrams updated 7 operating requirements operating conditions: tj = -25...110 c 8 description of functions pins res1/0 table corrected 9 ic-haus expressly reserves the right to change its products and/or specifcations. an infoletter gives details as to any amendments and additions made to the relevant current specifcations on our internet website www.ichaus.com/infoletter and is automatically generated and shall be sent to registered users by email. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. the data specifed is intended solely for the purpose of product description and shall represent the usual quality of the product. in case the specifcations contain obvious mistakes e.g. in writing or calculation, ic-haus reserves the right to correct the specifcation and no liability arises insofar that the specifcation was from a third party view obviously not reliable. there shall be no claims based on defects as to quality in cases of insignifcant deviations from the specifcations or in case of only minor impairment of usability. no representations or warranties, either expressed or implied, of merchantability, ftness for a particular purpose or of any other nature are made hereunder with respect to information/specifcation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus products are not designed for and must not be used in connection with any applications where the failure of such products would reasonably be expected to result in signifcant personal injury or death (safety-critical applications) without ic-haus specifc written consent. safety-critical applications include, without limitation, life support devices and systems. ic-haus products are not designed nor intended for use in military or aerospace applications or environments or in automotive applications unless specifcally designated for such use by ic-haus. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. software and its documentation is provided by ic-haus gmbh or contributors "as is" and is subject to the zvei general conditions for the supply of products and services with ic-haus amendments and the zvei software clause with ic-haus amendments ( www.ichaus.com/eula ). ? release date format: yyyy-mm-dd p r e l i m i n a r y p r e l i m i n a r y
ic-lfh series high-resolution linear image sensors rev b1, page 14/ 14 ordering information type package order designation ic-lfh320 obga lfh1c ic-lfh320 obga lfh1c IC-LFH640 obga lfh2c IC-LFH640 obga lfh2c ic-lfh960 obga lfh3c ic-lfh960 obga lfh3c ic-lfh1024 obga lfh5c ic-lfh1024 obga lfh5c please send your purchase orders to our order handling team: fax: +49 (0) 61 35 - 92 92 - 692 e-mail: dispo@ichaus.com for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (0) 61 35 - 92 92 - 0 am kuemmerling 18 fax: +49 (0) 61 35 - 92 92 - 192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.com/sales_partners p r e l i m i n a r y p r e l i m i n a r y

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